(1) Field of the Invention
The present invention relates to an alarm termination apparatus in which alarm bits from multi-channel data are written to or read from a bi-directionally accessible random access memory. The alarm termination apparatus is applied to a data communication system and intended to ensure an increased speed of writing/reading the alarm bits in association with the random access memory.
(2) Description of the Prior Art
A data communication system is designed to combine a plurality of channel data into a high-speed data stream and transmit the data stream on a transmission line. Simultaneously, the data communication system inserts alarm bits, which contain supervising control information for each channel, into the high-speed data stream for transmission. Some node of the data communication system is provided with an alarm termination unit. In the alarm termination unit, the alarm bits are sampled from the received data stream, and different alarm bits specific to that node are inserted into the output data stream.
With the development of recent data communication systems having high-speed data processing functions, it is desired that the alarm termination unit which terminates data in high-speed data streams have the ability to process the alarm data at higher speeds. It is desired that the alarm termination unit can be built in a smaller circuit size.
FIG. 1 shows a part of a data communication system including an alarm termination unit to which the present invention is applied. In FIG. 1, a high-speed serial input data stream from a transmission line is converted by a serial-to-parallel (S/P) conversion unit 1 into "n" pieces of parallel data for several internal processing steps in the data communication system. A frame sync (synchronizing) detecting unit 2 detects synchronization of the parallel data during a receive operation by using frame bits from the parallel data. An alarm bit sampling unit 3 takes out alarm bits from the parallel data output from the frame sync detecting unit 2, and transfers the alarm bits to an alarm termination unit 4. On the other hand, the parallel data from the frame sync detecting unit 2 is transferred to a data receiving part (not shown) through the alarm bit sampling unit 3 for a data receiving process by the data receiving part.
The alarm termination unit 4 has an internal random access memory (RAM) for storing the alarm bits. In the alarm termination unit 4, the alarm bits, taken out from the parallel data, are written to the RAM at memory locations each specified by the parallel data. Thereafter, the alarm bits are read out from the RAM, and a step of processing the alarm bits is performed in association with a control unit 5. The read-out alarm bits are either updated or unchanged in accordance with select pulses supplied from the control unit 5 during the step, and the resulting alarm bits are transferred to an alarm bit multiplex unit 6.
In the data communication system, transmit data which will be transmitted on a transmission line is supplied from a data transmitting part (not shown) to the alarm bit multiplex unit 6. In the alarm bit multiplex unit 6, the alarm bits from the alarm termination unit 4 and the transmit data from the data transmitting unit are multiplexed. A frame bit generating unit 7 generates frame bits and inserts them into the multiplexed data from the alarm bit multiplex unit 6. A parallel-to-serial (P/S) conversion unit 8 converts them into serial data streams, and they are transmitted on the transmission line as the output data of the data communication system.
FIG. 2 shows a conventional alarm termination unit of a data communication system. This alarm termination unit uses a plurality of flip-flop circuits to allow the speed of processing alarm data to be increased.
In FIG. 2, a RAM (random access memory) 10 has data ports A and data ports B, and the RAM 10 is bi-directionally accessible. In the RAM 10, for example, first data can be written to the data ports A of the memory and the first data can be read from the data ports A of the memory, and at the same time second data can be written to the data ports B of the memory and the data can be read from the data ports B of the memory. A write address unit 11 generates a write address at which an alarm bit is written to the ports A of the RAM 10. A read address unit 12 generates a read address at which an alarm bit is read from the ports A of the RAM 10. A write address unit 13 generates a write address at which an alarm bit is written to the ports B of the RAM 10. A read address unit 14 generates a read address at which an alarm bit is read from the ports B of the RAM 10.
In FIG. 2, a high-speed serial input data stream #1 is supplied to a serial-to-parallel (S/P) conversion unit 15. The S/P conversion unit 15 converts the high-speed serial input data stream #1 into "n" low-speed parallel inputs. The low-speed parallel inputs are sent to "n" flip-flop (FF) circuits 16, and the inputs are temporarily stored in the flip-flop circuits 16, respectively. The "n" parallel inputs stored in the flip-flop circuits 16 are simultaneously sent to the RAM 10 via a selector 17, and they are written to the ports A of the RAM 10, respectively.
The stored parallel inputs are read out from the ports A of the RAM 10, and they are sent to "n" flip-flop (FF) circuits 18 via the selector 17. The "n" pieces of the read data are temporarily stored in the flip-flop circuits 18, and they are simultaneously sent to a parallel-to-serial (P/S) conversion unit 19. The P/S conversion unit 19 converts the "n" pieces of the read data into a high-speed serial output data stream #1. Then, the high-speed serial output data stream #1 is transmitted on a transmission line.
In a similar manner, the stored parallel inputs are read out from the ports B of the RAM 10, and they are sent to "n" flip-flop (FF) circuits 21 via a selector 20. The "n" pieces of the read data are temporarily stored in the flip-flop circuits 21, and are simultaneously sent to a parallel-to-serial (P/S) conversion unit 22. The P/S conversion unit 22 converts the "n" pieces of the parallel data into a high-speed serial output data stream #2. Then, the high-speed serial output data stream #2 is transmitted on the transmission line.
On the other hand, a high-speed serial input data stream #2 is supplied to a serial-to-parallel (S/P) conversion unit 23. The S/P conversion unit 23 converts the high-speed serial input data stream #2 into "n" low-speed parallel inputs. The low-speed parallel inputs are sent to "n" flip-flop (FF) circuits 24, and the inputs are temporarily stored in the flip-flop circuits 24, respectively. The "n" parallel inputs stored in the flip-flop circuits 24 are simultaneously sent to the RAM 10 through the selector 20, and they are written to the ports B of the RAM 10.
The stored parallel inputs are read out from the ports B of the RAM 10, and they are sent to the flip-flop circuits 21 via the selector 20. The "n" pieces of the parallel data are temporarily stored in the flip-flop circuits 21, and they are simultaneously sent to the P/S conversion unit 22. The P/S conversion unit 22 converts the "n" pieces of the parallel data into a high-speed serial output data stream #2 for transmission.
Similarly, the stored parallel inputs are read out from the ports A of the RAM 10, and they are sent to the flip-flop circuits 18 via the selector 17. The "n" pieces of the parallel data are temporarily stored in the flip-flop circuits 18, and are simultaneously sent to the P/S conversion unit 19. The P/S conversion unit 19 converts the "n" pieces of the parallel data into a high-speed serial output data stream #1 for transmission.
During the read and write operations described above, the write address unit 11 sends a write address signal indicating a write address relating to the ports A, to the RAM 10 via an OR circuit 25, and the read address unit 12 sends a read address signal indicating a read address relating to the ports A, to the RAM 10 via the OR circuit 25. The write address unit 13 sends a write address signal indicating a write address relating to the ports B, to the RAM 10 via an OR circuit 26, and the read address unit 14 sends a read address signal indicating a read address relating to the ports B, to the RAM 10 via the OR circuit 26.
As described above, the stored alarm bits are read out from the RAM 10, and a step of processing the alarm bits is performed in association with the control unit 5. During the step, the read-out alarm bits are either updated or unchanged in accordance with select pulses from the control unit 5. When a select pulse indicating non-update is output from the control unit 5, the alarm bit is unchanged and it is transferred to the alarm bit multiplex unit 6 On the other hand, when a select pulse indicating update is output from the control unit 5, the alarm bit is updated and the updated alarm bit is transferred to the alarm bit multiplex unit 6.
The conventional alarm bit termination unit described above uses a bi-directionally accessible RAM and accepts different write addresses for the data ports A and B of the RAM during a write procedure. The unit also accepts different read addresses for the data ports A and B of the RAM during a read procedure. Therefore, it is necessary that the read procedure for the RAM is performed after the write procedure for the RAM is completed.
If the write and read procedures for the RAM are performed at the same time, the conventional alarm bit termination unit is in danger of erroneously deleting the content of the alarm information or losing it. The conventional alarm termination unit must perform the write procedure and the read procedure in separate operating cycles, in order to safely carry out the alarm termination task. Therefore, the conventional alarm bit termination unit inevitably requires a certain time delay to complete the alarm termination task.
In order to eliminate the time delay mentioned above, the conventional alarm termination unit uses a plurality of flip-flop circuits for both the inputs and the outputs. With the use of the plurality of flip-flop circuits in the alarm termination unit, the "n" pieces of the parallel data are temporarily stored in the flip-flop circuits, and are simultaneously written to the RAM, in order to allow the rate of processing the alarm bits to be increased. Because of the many flip-flop circuits, it is necessary that the conventional alarm termination unit have a large circuit size. In addition, the conventional alarm termination unit includes the write and read address units 11 and 12 for the ports A and the write and read address units 13 and 14 for the ports B. Because of the many address units, it is necessary that the conventional alarm termination unit have a large circuit size.